Detailansicht
Generating Hardware Assertion Checkers
For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
ISBN/EAN: 9781402085857
Umbreit-Nr.: 1932515
Sprache:
Englisch
Umfang: xx, 280 S.
Format in cm:
Einband:
gebundenes Buch
Erschienen am 03.07.2008
Auflage: 1/2008
- Zusatztext
- Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an "under-the-hood" view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.
- Kurztext
- Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an "under-the-hood" view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. The PSL and SVA languages are treated in a unified way, thereby facilitating better learning and usage of the modern assertion languages, with a focus on obtaining the highest performance from assertion checkers. The obtained checkers are thoroughly benchmarked and verified, while formal proofs using automated reasoning techniques are explained. Included are examples of practical circuits (PCI, AMBA, Wishbone-PIC, CPU Pipeline) and their assertion checker synthesis.
- Autorenportrait
- Inhaltsangabe1 Introduction. 1.1 Context and Motivation. 1.2 Book Objectives. 1.3 Overview of the Book. 1.4 External Contributions and Collaborations. 2 Assertions and the Verification Landscape. 2.1 Origins of Assertions: Software Checking. 2.2 Uses of Assertions in Hardware. 2.3 Assertion Checkers and Checker Generators. 2.4 Assertion Support in Simulators and Emulators. 2.5 Checkers in Silicon Debugging. 2.6 Assertions in Static and Dynamic Verification. 2.7 Supported Simulation and Emulation Semantics. 3 Basic Techniques Behind Assertion Checkers. 3.1 Background. 3.2 Modular Approach to Checker Generation. 3.3 Automata-Based Approach to Checker Generation. 3.4 Other Related Research. 4 PSL and SVA Assertion Languages. 4.1 The Property Specification Language. 4.2 SystemVerilog Assertions. 5 Automata for Assertion Checkers. 5.1 Introduction and Overview. 5.2 Automaton Framework. 5.3 Generating Circuit-Level Checkers from Assertion Automata. 6 Construction of PSL Assertion Checkers. 6.1 Introduction and Overview. 6.2 Automata Construction for Booleans. 6.3 Automata Construction for Sequences. 6.4 Automata Construction for Properties. 6.5 Automata Construction for Verification Directives. 7 Enhanced Features and Uses of PSL Checkers. 7.1 Introduction and Overview. 7.2 Recursive Compilation Strategies. 7.3 A Special Case for eventually! 7.4 Debug Enhancements for Checkers. 7.5 Checkers in Silicon Debug and On-Line Monitoring. 8 Evaluating and Verifying PSL Assertion Checkers. 8.1 Introduction and Overview. 8.2 Non-Synthetic Assertions. 8.3 Evaluating Assertion Grouping. 8.4 Pre-Synthesis Results. 8.5 Benchmarking Debug Enhancements. 8.6 Benchmarking Sequences and Properties. 9 Checkers for SystemVerilog Assertions. 9.1 Introduction and Overview. 9.2 Checker Generation for SystemVerilog Assertions. 9.3 Experimental Results for SVA Checkers. 10 Conclusions and FutureWork. 10.1 Conclusion. 10.2 FutureWork. A Example for Up-down Counter. References. Index.