Detailansicht
Functional Design Errors in Digital Circuits
Diagnosis Correction and Layout Repair - Lecture Notes in Electrical Engineering 32, Lecture Notes in Electrical Engineering 32
ISBN/EAN: 9781402093647
Umbreit-Nr.: 1369663
Sprache:
Englisch
Umfang: xxiv, 200 S.
Format in cm:
Einband:
gebundenes Buch
Erschienen am 10.12.2008
Auflage: 1/2009
- Zusatztext
- Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices.
- Kurztext
- Due to the dramatic increase in design complexity, modern circuits are often produced with functional errors. While improvements in verification allow engineers to find more errors, fixing these errors remains a manual and challenging task. Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. In addition, Functional Design Errors in Digital Circuits Diagnosis describes a comprehensive evaluation of spare-cell insertion methods. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices.
- Autorenportrait
- InhaltsangabeDedication. List of Figures. List of Tables. Preface. Part I Background and Prior Art. 1. INTRODUCTION. 1.1 Design Trends and Challenges. 1.2 State of the Art. 1.3 Our Approach. 1.4 Key Innovations and Book Outline. 2. CURRENT LANDSCAPE IN DESIGN AND VERIFICATION. 2.1 Front-End Design. 2.2 Back-End Logic Design. 2.3 Back-End Physical Design. 2.4 Post-Silicon Debugging. 3. FINDING BUGS AND REPAIRING CIRCUITS. 3.1 Simulation-Based Verification. 3.2 Formal Verification. 3.3 Design for Debugging and Post-Silicon Metal Fix. Part II FogClearMethodologies and Theoretical Advances in Error Repair. 4. CIRCUIT DESIGN AND VERIFICATION METHODOLOGIES. 4.1 Front-End Design. 4.2 Back-End Logic Design. 4.3 Back-End Physical Design. 4.4 Post-Silicon Debugging. 5. COUNTEREXAMPLE-GUIDED ERROR-REPAIR FRAMEWORK. 5.1 Background. 5.2 Error-Correction Framework for Combinational Circuits. 6. SIGNATUREBASED RESYNTHESIS TECHNIQUES. 6.1 Pairs of Bits to be Distinguished (PBDs). 6.2 Resynthesis Using DistinguishingPower Search. 6.3 Resynthesis Using GoalDirected Search. 7. SYMMETRYBASED REWIRING. 7.1 Background. 7.2 Exhaustive Search for Functional Symmetries. 7.3 PostPlacement Rewiring. 7.4 Experimental Results. 7.5 Summary. Part III FogClear Components. 8. BUG TRACE MINIMIZATION. 8.1 Background and PreviousWork. 8.2 Analysis of Bug Traces. 8.3 Proposed Techniques. 8.4 Implementation Insights. 8.5 Experimental Results. 8.6 Summary. 9. FUNCTIONAL ERROR DIAGNOSIS AND CORRECTION. 9.1 Gate-Level Error Repair for Sequential Circuits. 9.2 Register-Transfer-Level Error Repair. 9.3 Experimental Results. 9.4 Summary. 10. INCREMENTAL VERIFICATION FOR PHYSICAL SYNTHESIS. 10.1 Background. 10.2 Incremental Verification. 10.3 Experimental Results. 10.4 Summary. 11. POSTSILICON DEBUGGING AND LAYOUT REPAIR. 11.1 Physical Safeness and Logical Soundness. 11.2 New Resynthesis TechniqueSafeResynth. 11.3 PhysicallyAware Functional Error Repair. 11.4 Automating Electrical Error Repair. 11.5 Experimental Results. 11.6 Summary. 12. METHODOLOGIES FOR SPARE-CELL INSERTION. 12.1 Existing Spare-Cell Insertion Methods. 12.2 Cell Type Analysis. 12.3 Placement Analysis. 12.4 Our Methodology. 12.5 Experimental Results. 12.6 Summary. 13. CONCLUSIONS. Index. References.